1. Field of the Invention
The present invention generally relates to methods for generating a standard reference die for use in a die to standard reference die inspection and methods for inspecting a wafer. Certain embodiments relate to a computer-implemented method for generating a standard reference die for use in a die to standard reference die inspection that includes combining output of an inspection system for a centrally located die on a wafer and one or more dies located on the wafer based on within die positions of the output.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield in the manufacturing process and thus higher profits. Inspection has always been an important part of fabricating semiconductor devices such as ICs. However, as the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of acceptable semiconductor devices because smaller defects can cause the devices to fail. For instance, as the dimensions of semiconductor devices decrease, detection of defects of decreasing size has become necessary since even relatively small defects may cause unwanted aberrations in the semiconductor devices.
As design rules shrink, semiconductor manufacturing processes may also be operating closer to the limitations on the performance capability of the processes. In addition, at smaller design rules, process induced failures may, in some cases, tend to be systematic. That is, process induced failures tend to fail at predetermined design patterns often repeated many times within the design. Detection and elimination of spatially systematic, electrically relevant defects is important because eliminating such defects can have a significant overall impact on yield.
However, detection of systematic and other repeater defects using inspection techniques such as die-to-die inspection and die to standard reference die inspection are disadvantageous for a number of reasons. For example, although die-to-die inspection techniques have achieved wide spread success in wafer inspection for detection of random defects, by their very nature such inspection techniques are unable to detect systematic and repeater defects. In particular, by comparing two test die to each other, systematic and repeater defects that occur in both test die cannot be detected. In addition, die to standard reference die inspection techniques have been adopted much less than die-to-die inspection techniques in semiconductor manufacturing related applications because it is often difficult to acquire a suitable standard reference die. For example, unlike die-to-die inspection techniques in which the output for the dies that are compared is typically acquired in the same inspection scan of a wafer, die to standard reference die techniques often are complicated due to differences between the test die and the standard reference die (or the test wafer and the standard reference wafer) such as color variations and due to the difficulty in achieving relatively accurate alignment between the test die and the standard reference die.
Accordingly, it would be advantageous to develop methods for generating a standard reference die for use in a die to standard reference die inspection and methods for inspecting a wafer using die to standard die reference inspection techniques that can be used to detect repeater (systematic) defects with relatively high accuracy for applications such as single die reticle inspection and process window qualification (PWQ) applications.